It is well known that the a voltage ratio between an input voltage and an output voltage in a (capacitive) DC-to-DC converter is dependent on the capacitance of the converter.
It is further well known that the capacitance of a capacitor device scales with the area of the capacitor electrodes, with the dielectric constant of the dielectric material between the capacitor electrodes, and with the inverse of the distance between the capacitor electrodes.
To increase the area of the capacitor electrodes comprised in electronic devices, which are formed by integrated circuits on a semiconductor chip, trench capacitors have widely been used. In a trench capacitor, the electrodes are formed by electrically conductive layers deposited in a trench, recess or pore prepared in the substrate (wafer). A pore or trench can for instance be made by locally etching the substrate. The production of dense arrays of such features is well known. Electrode layers can be formed in the pores by known deposition techniques, such as low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The electrically conductive layers are electrically isolated from each other and from the substrate by interposed dielectric layers.
A pore filled in this way to form a trench capacitor typically has a general shape resembling the letter “U” in a cross-sectional view. It is known to arrange a large number of pores in a substrate, in the form of a pore array, and to deposit step-conformal, that is, uniformly thick electrode layers in all pores in an attempt to achieve high capacitance values in electronic devices containing trench capacitors. A capacitance density, defined as a capacitance per unit area, is used to characterize such trench capacitor devices. Capacitance density values of about 30 nF/mm2 with a breakdown voltage of 30 V can be achieved using MOS (Metal-Oxide-Semiconductor)/MIS (Metal-Insulator-Metal) capacitor layer stacks grown in pore arrays etched in a high-surface area silicon substrate, see WO2004/114397.
Double and triple-layer-stack trench capacitors are known from DRAM (dynamic random access memory) applications, see US2004/0228067 and U.S. Pat. No. 6,897,508 B2, respectively. However, the trench capacitor structures described in these documents are designed for operation at low voltages, typically in the range of a few Volts. In addition, trench capacitors in DRAM applications require a refresh of the stored charge amount several times per second, which is not acceptable in applications involving higher voltages in the range of tens of Volt, or higher-frequency signals, like radio-frequency (RF) signals. DRAM memory devices further have trench capacitors that are optimised for a small, i.e., deep submicrometer pitch between adjacent pores in the substrate.
US 2003/0213989 A1 describes a trench capacitor device, which, in a cross-sectional view has two rectangular-shaped trench capacitors with a filling in the form of a metal-polysilicon-dielectric-polysilicon layer sequence. According to this document, high capacitance density values between 30 and 100 nF/mm2 can be achieved with this structure, when using dielectric layers made from the high-k dielectric material Ta2O5. The electrodes of the trench capacitor of US 2003/0213989 are independent from the potential of the substrate.
Use of this type of capacitor for different application purposes having different capacitive requirements, that may even vary in time during operation, is not possible.